Hardware

Advanced ASIC, VLSI, and Mixed-Signal Implementation

A graduate-level course covering the full ASIC design stack: RTL microarchitecture, UVM verification, synthesis, static timing analysis, physical design, mixed-signal interfaces, and low-power techniques, culminating in a portfolio-grade accelerator block.

RTL Design, Verification, and Hardware Debugging

A junior/senior undergraduate pathway into digital hardware design and verification, built around SystemVerilog, open-source HDL simulators, and NVIDIA-aligned skills across ASIC design, verification, synthesis, and static timing analysis.